As semiconductor device packing densities become higher, cells in the semiconductor device become smaller to increase an internal field intensity. The increased field intensity accelerates carriers in a depletion layer in the vicinity of a drain during operation of the device to cause a hot carrier effect in which the carriers are injected from a channel region to a gate oxide film. The carriers injected in the gate oxide film form a potential at an interface of a semiconductor substrate and the gate oxide film, leading to change a threshold voltage (VTH) or drop a mutual conductance, which makes device characteristics poor. Therefore, to prevent the device characteristics from becoming poor due to the hot carrier effect, it is required to change a drain structure, like an LDD (Lightly Doped Drain).
FIGS. 1A˜1C illustrate sections showing a known method for fabricating a MOS transistor of a typical LDD structure in a semiconductor device. Referring to FIG. 1A, a field oxide film (not shown), an active cell isolation film, is formed on a surface of a P-type semiconductor substrate 100 of silicon or the like by LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation) for defining an active region and field region of cells.
A portion of the substrate at the active region is removed by photolithography to form a trench where a gate is to be formed. Then, ions are injected into an entire exposed surface of the substrate for adjusting a threshold voltage. A surface of the semiconductor substrate 100 inclusive of the trench is subjected to thermal oxidation to form an oxide film 102 for forming a gate insulating film. Then, a polysilicon layer 104 is deposited on the field oxide film and the oxide film 102 by Chemical Vapor Deposition (CVD) for forming a gate. In this instance, in deposition of the polysilicon layer 104, doped silicon may be used, or undoped silicon may be used, when the polysilicon layer 104 is doped by ion injection or the like, to make the polysilicon layer conductive.
Referring to FIG. 1B, a coat of photoresist is applied onto the polysilicon layer 104, and subjected to exposure and development with a mask that defines the gate to form a photoresist pattern (not shown) covering a region where the gate is to be formed. Then, the polysilicon layer for forming the gate, and the oxide film for forming the gate insulating film, which are not protected with the photoresist pattern, are removed by anisotropic etching, such as dry etching, to form a gate pattern 104. Because the gate pattern 104 is in the trench, an effective channel length of a transistor to be formed later increases. Additionally, because the gate pattern 104 has a topography partially projected from the surface of the substrate, a height difference of step from neighboring portions can be improved.
Then, N-type impurity ions are injected into the substrate 100 at an exposed active region by using the gate pattern 104 as an ion injection mask to form lightly doped impurity ion buried layers on opposite sides of the gate pattern. The lightly doped impurity ion buried layers form lightly doped impurity diffusion regions 106 of LDD structures.
Referring to FIG. 1C, an insulating layer, such as an oxide silicon film or a nitride film, is deposited on the substrate to cover the gate pattern 104, and etched back to expose the surface of the semiconductor substrate 100, to form sidewall spacers 108. The sidewall spacers 108 insulates the gate 104 from surroundings, and is used as an ion injection mask for forming heavily doped impurity diffusion regions 110 of the source/drain.
N-type impurity ions are injected into the semiconductor substrate at an exposed active region by using the gate pattern 104 and the sidewall spacers 108 as an ion injection mask to form buried heavily doped impurity diffusion regions used as source/drain regions. In this instance, most of the buried heavily doped impurity diffusion regions respectively overlap with the buried lightly doped impurity diffusion regions, except portions under the sidewall spacers 108 where only the buried lightly doped impurity diffusion regions exist.
Then, the substrate 100 having the buried heavily doped impurity diffusion regions and the buried lightly doped impurity diffusion regions formed therein are subjected to heat treatment, such as annealing, to diffuse the impurity ions for forming source/drain junctions, to form the lightly doped impurity diffusion regions 106 and the heavily doped impurity diffusion regions 110. In this instance, because the annealing is performed at an elevated temperature, the impurities can be diffused from the gate 104 and the source/drain regions 110 outwardly to increase a resistance.